Dr. Vijay Nath

S. No.

Authors Name

Paper Title

Name of Conference/Symposium/ Workshop

Duration with Year

Name of Organizing Institutes

Pankaj Singh,

Neema Bhandari,

Shilpi Bisht,

Vijay Nath &

 Sudhir Sharma

Energy-Efficient Design of Internet of Health Things Enabled Blood Pressure Monitoring Wristband Sensor

2^nd  International Conference on Nano electronics, Machine learning, Internet of Things & Computing Systems (NMIC - 2022)

(Best Paper Award)

23-24^th

April 2022

ISVE & ARTTC BSNL Ranchi

Shashwat Jha, Vishvaditya Luhach, and Vijay Nath

Power transmission line classification through Artificial Intelligence: Application of Transfer Learning and Deep Convolution Learning Technique

7^th  International Conference

Nanoelectronics, Circuits & Communication Systems (NCCS-2021)

(Best Paper Award)

29-30^th

Jan 2022

ISVE & ARTTC BSNL Ranchi

Vijay Nath

For Fostering the Ecosystem Bridging Government, Academia and Industry

Texas Instrumentation Embedded System Design using MSP430TM  MCU MOC 

(Certificate for Appreciation)

30^st Oct. 2021

Texas Instrumentation & AICTE New Delhi

Namrata Yadav, Mohd Javed Khan, Deepak Prasad, Abhishek Pandey,

Vijay Nath

Design of Ultra Low Power CMOS RF Front End Receiver Circuit for GPS Applications

Cadence Design Contest 2016

(Finalists in PG Category)

20^th May 2016

Cadence Design Systems India Pvt Ltd.

Plot 57A, B & C

Noida Special Economic Zone (NSEZ)

Noida 201305

Vijay Nath

One Day Workshop & Seminar on Electronic System Design & Manufacturing (ESDM-2015)

Funded by MoCIT MHRD New Delhi

Rs 15000/- each centre

ESDM program conducted at 15 places under aegis of IETE New Delhi e.g.

IIT Patna, NIT Arunachal Pradesh, IIT Guwahati, BIT Patna, BIT Deoghar, CIT Ranchi, Ranchi University, RPCIT Patna, NSIT Patna, MACET Patna, TIT Tripura, NIT Tripura, etc

(Program Coordinator, East Zone of India)

Session 1^st July 2014 to 30^th June 2015

MHRD New Delhi under aegis of IETE New Delhi

Dipayan Gosh,

Jyoti Singh, Ramkrishna Kundu,

Vijay Nath

Ultra Low Power CMOS OP-AMP Based Class-E Power Amplifier

Cadence Design Contest 2014

(Open Project Category)

Top6 in Master Category

1^st July 2014

Cadence Design Systems (I) Pvt Ltd

Level 2, Campus 3B

RMZ Ecospace

Sarjapur Outer Ring Road

Bangalore 560 037

Ramkrishna Kundu,

Abhishek Pandey,

Dipayan Ghosh

Vijay Nath

Layout Design of CMOS Operational Amplifier

IEI Technical Contest and Convocation-2013

(First Prize)

19^th Oct 2013

IEI Kerala Center, Trivandrum

Deepak Prasad,

Vijay Nath

Design of Ultra Low Power CMOS Temperature Sensors Cell for Missiles Applications

3^rd International Conference Computing Communication & Sensor Network (CCSN-2013)

(Best Paper Award)

22-24^th Nov 2013

IEI, ISTM, & IEEE Kolkata

Vijay Nath

Manish Mishra, K.S. Yadav

Design & Development of CMOS Signal Conditioning Circuit for MEMS Sensors

6^th Conference of the International Academy of Physical Sciences on Emerging Dimensions of Physical Sciences

(Young Scientist Award-2004)

6-8^th Feb2004

DDU University Gorakhpur

Vijay Nath,

K. Suleman,

K.S. Yadav,

Samim Ahmad

Layout Design of CMOS Signal Conditioning Circuit for Piezo-resistive Pressure Sensors

VIVEKANANDA TECHNO FEISTA 2002

(First Prize)

11-12^th Jan 2002

UPTU, Lucknow

(Radha Govind  Engg College & Institute of Informatics & Management Sciences, Meerut)