List of Publications

Book Chapters:

1. Sharma, J., Sharma, P., Verma, D. (2025). Performance Comparison of 45 nm CMOS Based CDTA and 32 nm FinFET Based CDTA and Its Application as Universal Filter. In: Bhowmik, P.S., Bohre, A.K., Kirar, M.K., Kolhe, M.L., Suwarno, S. (eds) Application of Advance Techniques in Power and Energy Systems. CISTEE 2023. Lecture Notes in Electrical Engineering, vol 1305. Springer, Singapore. https://doi.org/10.1007/978-981-96-0476-0_13.
2. Sharma, P., Sharma, J., Sharma, R., Janyani, V., Verma, D. (2025). A Cervical Spine Motion Range Detection System Using MwCNTs-PDMS Based Sensor. In: Bhowmik, P.S., Bohre, A.K., Kirar, M.K., Kolhe, M.L., Suwarno, S. (eds) Application of Advance Techniques in Power and Energy Systems. CISTEE 2023. Lecture Notes in Electrical Engineering, vol 1305. Springer, Singapore. https://doi.org/10.1007/978-981-96-0476-0_22.
3. Sharma, J., Ahmad, R., Varma, T., Boolchandani, D. (2025). A 0.1–4.71 GHz Integer-N CP-PLL-Based Low-Power Frequency Synthesizer for High-Speed Applications. In: Gupta, A., Pandey, J.G., Chaturvedi, N., Dwivedi, D. (eds) Emerging VLSI Devices, Circuits and Architectures. VDAT 2023. Lecture Notes in Electrical Engineering, vol 1234. Springer, Singapore. https://doi.org/10.1007/978-981-97-5269-0_3.
4. Kumawat, M., Mathur, A., Sharma, J., Srinivasulu, A. “An Integrator Using Voltage Differencing Transconductance Amplifier,” In Proceedings of 6th International Conference on Recent Trends in Computing. Lecture Notes in Networks and Systems, vol 177. Springer, (2021), Singapore. https://doi.org/10.1007/978-981-33-4501-0_1
5. Jyoti Sharma, Ritambhara and Avireni Srinivasulu, “A Novel CNFET Based CCCDTA and Its Application as a Schmitt Trigger” Advances in Smart Grid Automation and Industry 4.0, Lecture Notes in Electrical Engineering, vol 693. Springer, Singapore (2021), https://doi.org/10.1007/978-981-15-7675-1
6. Anushree Mathur, Mrinalini Kumawat, Jyoti Sharma and Avireni Srinivasulu, “A Schmitt Trigger by means of a Voltage Differencing Transconductance Amplifier Advances in Smart Grid Automation and Industry 4.0, Lecture Notes in Electrical Engineering, vol 693. Springer, Singapore, (2021), https://doi.org/10.1007/978-981-15-7675-1
7. Jyoti Sharma, Mohd. Samar Ansari, and Sudip Kundu, “Tunable Universal Filter in ±0.5V 32nm CNFET for ISM 2.4 GHz Bluetooth/Zigbee Transceivers”, Advances in Intelligent Systems and Computing book series of Springer, Vol. 624, 2018, ISBN: 978-981-10-5903-2_3 (Print) 978-981-10-1708-7(Online),  10.1007/978-981-10-5903-2_3
8. Jyoti Sharma and Mohd. Samar Ansari, “Low THD ±0.75V 32nm CNFET Quadrature VCO for PLL and Costas-Loop Applications,” Advances in Intelligent Systems and Computing book series of Springer, Vol. 479, 2017, ISBN: 978-981-10-1707-0 (Print) 978-981-10-1708-7 (Online), 10.1007/978-981-10-1708-7_54

SCI Journals:

1. Singhal, A., Sharma, J., Rajput, D.S. et al. Optimization of performance parameters of differential ring oscillator using Taguchi DoE and Pareto ANOVA techniques for fast-setting PLL frequency synthesizer. Analog Integr Circ Sig Process 124, 59 (2025). https://doi.org/10.1007/s10470-025-02468-z
2. Sharma, J., Singhal, A., Varma, T. et al. Design and Optimization of a Symmetrical Phase-Frequency Detector (SPFD) Through Statistical Techniques. Circuits Syst Signal Process (2025). https://doi.org/10.1007/s00034-025-03030-y, 11.02.2025
3. Jyoti Sharma, Riyaz Ahmad, Ashutosh Yadav, Tarun Varma and Dharmendar Boolchandani, “Design and Optimization of Phase Frequency Detector through Taguchi and ANOVA Statistical Techniques for Fast Settling Low Power Frequency Synthesizer,” Integration, The VLSI Journal, Vol. 96, May 2024, 102162, https://doi.org/10.1016/j.vlsi.2024.102162
4. Jyoti Sharma, Gaurav Kumar Sharma, Tarun Varma and Dharmendar Boolchandani, “Optimization of performance parameters of phase frequency detector using Taguchi DoE and Pareto ANOVA techniques,” Journal of Circuits, Systems, and Computers, Vol. 32, No. 09, (2023) 2350158, https://doi.org/10.1142/S021812662350158X
5. Jyoti Sharma, Gaurav Kumar Sharma, Tarun Varma and Dharmendar Boolchandani, “A high speed phase detection circuit with no dead zone suitable for minimal jitter and low power applications,” Journal of Circuits, Systems, and Computers, Vol. 31, No. 15, (2022) 2250267, https://doi.org/10.1142/S021812662250267X

SCOPUS Journals:

1. Dua T., Kumawat, R., Singh N., Sharma, J., and Srinivasulu. “High Speed Energy Efficient Latch Architectures for Sequential Circuit Design”, Journal of VLSI Circuits and Systems, 7(1), 22 March 2025, 19-24, ISSN: 2582-1458
2. Rajput, A., Kumawat, R., Sharma, J., and Srinivasulu, A. “Design of Novel High Speed Energy Efficient Robust 4:2 Compressor,” Journal of VLSI Circuits and Systems, 6(2), 10 June 2024, 53–64, https://doi.org/10.31838/jvcs/06.02.06
3. Komal Shrivastavaa, Parul Garg,  Avireni Srinivasulu and Jyoti Sharma, “A Sense Amplifier Based Modified Low Voltage Two Stage Flip-Flop with CNTFETs”, ECS Transactions, Volume 107, Number 1, April 2022 (SCOPUS),  10.1149/10701.19517ecst, IF:0.7
4. Avireni Bhargava, J. K. Saini, Jyoti Sharma and K. M. Santhoshini, “A Review Article on Integrator Circuits Using Various Active Devices”, Journal of Advance Research in Dynamical & Control Systems, Vol. 11, 26-32, 07-Special Issue, 2019 (SCOPUS).
5. Jyoti Sharma, Shantanu Chakraborty: MOCCCDTA-based Current Mode Tunable Universal Biquad Filter for Bluetooth Applications. International Journal of Electrical and Computer Engineering(IJECE), Vol 6, No 4: August 2016 (SCOPUS), http://doi.org/10.11591/ijece.v6i4.pp1499-1505

International Journals:

1. Jyoti Sharma, Saket Jhalani  and Lakshya Dwivedi: Designing of Current-Mode Active Filter Using 45nm CMOS-Based CCII. IOSR Journal of VLSI and Signal Processing (IOSR-JVSP), Volume 6, Issue 2, pp 66-72, I(Mar-Apr. 2016).
2. Jyoti Sharma and Kshitij Sharma: Performance Evaluation of Electronically Tunable Filter Using CCCII in 45nm CMOS Technology for Wi-Fi Applications. International Journal of Science and Research (IJSR) ,Volume 5 Issue 3, 2053-2057, March 2016.
3. Jyoti Sharma and Anchal Sharma. Article: Universal Filter Design using 45nm CMOS-based DDCC for Bluetooth/ Zigbee Applications. International Journal of Computer Applications 134(13):36-40, January 2016. Published by Foundation of Computer Science (FCS), NY, USA.

International Conferences:

1. Jyoti Sharma, Archana Singhal, Tarun Varma and Dharmendar Boolchandani, “Design and Evaluation of a Power Efficient Phase-Frequency Detector with PVT Tolerance in 45 nm CMOS Technology”, 3rd International Conference on Power Electronics, Intelligent Control, and Energy Systems (IEEE-ICPEICES-2024), DTU, Delhi, 26th -28th April, 2024.
2. A. Singhal, J. Sharma, D. S. Rajput, D. Boolchandani and C. Periasamy, "Design and Analysis of Fast Settling Wideband PLL Using a Novel Low Mismatch Current Charge Pump," 2024 IEEE Third International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES), Delhi, India, 2024, pp. 1045-1049, doi: 10.1109/ICPEICES62430.2024.10719110.
3. Jyoti Sharma and Puneet Sharma, “A comprehensive review of phase frequency detectors: Types, Characteristics and Applications”, Recent Trends in Engineering and Sciences (RTES-2023), May 02-03, 2023, SVNIT Surat, India.
4. Jyoti Sharma, Tarun Varma and Dharmendra Boolchandani, "A brief review of the various phase-frequency detector architectures," 2021 IEEE International Symposium on Smart Electronic Systems (iSES), 2021, pp. 74-78, doi: 10.1109/iSES52644.2021.00028.
5. Apoorva Agarwal and Jyoti Sharma, “CMOS cum CNFET Based High Performance Differential Amplifier for Nanoelectronics”, International Conference on Recent Innovations in Engineering and Technology, 18-19 February, 2017, MAIET, Jaipur.
6. Sharma, Jyoti; Ansari, Mohd. Samar; Sharma, Jankiballabh, "Electronically Tunable Resistor-less Universal Filter in ±0.5V 32nm CNFET," Electronic System Design (ISED), 2014 Fifth International Symposium on , vol., no., pp.206,207, 15-17 Dec. 2014   doi: 10.1109/ISED.2014.50    ISBN No. 978-1-4799-6964-7. Available on IEEE Xplore.
7. Sharma, J.; Ansari, M.S.; Sharma, J., "Current-Mode Electronically Tunable Resistor-less Universal Filter in ±0.5V 32Nm CNFET,"Devices, Circuits and Communications (ICDCCom), 2014 International Conference on , vol., no., pp.1,6, 12-13 Sept. 2014  doi: 10.1109/ICDCCom.2014.7024710 ISBN No. 978-1-4799-6052-1. Available on IEEE Xplore.

National Conferences:

1. Saket Jhalani, Kshitij Sharma and Jyoti Sharma, “Comparison & Implementation of CCCII in 45nm CMOS for design of Oscillator” National Conference on New Vistas of Development in Communication Technology (NVDCT-2016), MAIET, Jaipur, 9^th &11^th , April, 2016.
2. Shantanu Chakraborty and Jyoti Sharma, “ Design of Universal filter using CDTA in 45nm CMOS Technology”, National Conference on New Vistas of Development in Communication Technology (NVDCT-2016), MAIET, Jaipur, 9^th &11^th , April, 2016.
3. Rohit Taxak and Jyoti Sharma, “Performance Evaluation of ICCII using CMOS and CNFET Technology”, National Conference on Recent Technological Developments in Electronics and Electrical Engineering(RTDEEE-2016), JECRC, Jaipur, 12-13, August, 2016.

Invited Talks:

1. Delivered an invited talk on “Advances in VLSI Design: Techniques and Emerging Technologies” in the 'Demystifying VLSI Technology' lecture series, organized by the Department of Electronics and Communication, JECRC, Jaipur in collaboration with the IEEE Rajasthan Subsection and IEEE WIE Delhi Section on 07/04/025.
2. Hands-on training on LaTeX in 5-day online workshop on “Scientific Writing using LaTeX and Publication Ethics (SWLPE-2025)” organized at BIT Mesra, Jaipur Campus during 17th – 21st March 2025.

Workshops organised:

1. Convenor of 5 day online workshop on Scientific Writing using LaTeX and Publication Ethics organised at BIT Mesra, Jaipur Campus during 17th – 21st March 2025. 
2. Coordinator in  “Short Term Training Programme on VLSI Design using CADENCE Tool,” 20/02/2024- 21/03/2024 (one month).

Workshops/ FDPs attended:

1. One week online FDP on VLSI Testing and Testability, jointly organized by Electronics & ICT Academy, MNIT Jaipur from 14^th July, 2025- 21^st July, 2025.
2. One week (40-hour) online training program cum FDP on Foundations of VLSI Design Verification, jointly organized by Electronics & ICT Academy, MNIT Jaipur, IIITDM Jabalpur, IIT Roorkee and NIT Patna from 23^th June, 2025- 5^th July, 2025.
3. Two weeks online FDP on Semiconductor Devices Circuits & Sensor: Applications & Research Perspective, jointly organized by Electronics & ICT Academy, NIT Patna, IIITDM Jabalpur, MNIT Jaipur, IIT Kanpur and IIT Roorkee by the MeitY, Government of India from 9^th June, 2025- 20^th June, 2025.
4. One week UHV-II Course on Inculcating Universal Human Values in Technical Education, organized by AICTE, 25th to 30th December, 2024
5. Five days workshop on Emerging Cutting Edge Technologies in CMOS: Trends and Challenges, organized by NIT, Silchar, Assam, 11^th to 15^th December 2024.
6. One week UHV-I Course on Inculcating Universal Human Values in Technical Education, organized by AICTE, 4th to 8th December, 2023.
7. Two days FDP workshop on Recent Trends in MEMS for 6G Communications(RTMC-2023) organized by CSIR-CEERI, Jaipur Centre, August 17-18, 2023.
8. One-week workshop on VLSI to System Design: Silicon to End Application Approach organized by AICTE, Arm Education and STMicroelectronics, July 31st to 4th August, 2023.
9. One week outreach programme on Microelectronics and VLSI Design (MVD-2023) held during 15th -19th May 2023, organized by Department of Electronics and Communication Engineering, BIT Mesra, Ranchi.
10. Two Week Online Faculty Development Program/Short term Training Program on Advanced Optimization Techniques and hands-on with MATLAB/SCILAB (AOT 2022), Supported by Ministry of Electronics and Information Technology (MeitY), Electronics & ICT Academies at MNIT Jaipur, NIT Patna & IIITDM Jabalpur,  August 8 – 19, 2022.
11. One week online STTP on Emerging Tools and Techniques in VLSI, MEMS & MOEMS, Swami Keshvanand Institute of Technology, Management & Gramothan, Jaipur, 25/1/2022 to 29/1/2022.
12. Online training Programme on Digital Tools for Writing, Authoring and Reviewing Manuscripts, Supported by Ministry of Electronics and Information Technology (MeitY) , Electronics & ICT Academies MNIT Jaipur, NIT Patna & IIT Guwahati, 21st September and 2nd October 2020.
13. Webinar on Issues in Nanoscale VLSI Circuit Design organized by Department of Electronics Engineering, University Departments, Rajasthan Technical University, Kota on 5 September 2020.
14. TEQIP-III sponsored webinar on Gender Equality and Women Rights, organized by RTU, Kota and Poornima College of Engineering , Jaipur on 17 July 2020.
15. Nine Weeks course on Introduction to Programming with MATLAB, Coursera, Vanderbilt University, June-July, 2020.
16. One week FDP on Tools and Techniques for Research  in Engineering & Management, VGU, Jaipur, 23/06/2020-27/06/2020.
17. Webinar on  Effective Research Manuscript Writing organized by Manipal University, Jaipur on 16-Jun-2020.
18. Webinar on Art and Challenges of Writing Papers for IEEE Transactions organized by IEEE Banglore Section on 08 June, 2020.
19. Webinar on Recend Trends & Challenges in VLSI Design Techniques organized by Poornima College of Engineering, Jaipur on June 08, 2020.
20. One Professional Development Hour by attending Webinar on Endofullerenes: Nano-scale test tubes for single molecules and atoms organized by The National Academy of Sciences, India (NASI) - Delhi Chapter &MHRD-Institution Innovation Council (IIC) Deen Dayal Upadhyaya College Chapter on June 08, 2020.
21. Webinar on Education for Gen Z organized by Manipal University, Jaipur on 06-Jun-2020.
22. One Professional Development Hour by IEEE Electron Device Society (EDS) Distinguished Lecture (DL) on FOSS TCAD/EDA tools for Compact/SPICE Modeling on June 03, 2020.
23. One week Academy Training Programme on Latex and Technical Writing, MNIT, Jaipur, January 24-28,2018.
24. Eight weeks course on Digital Signal Processing, NPTEL, IIT Kharagpur, July to September 2016.
25. One week Academy Training Programme on Digital CMOS Devices & Circuits, MNIT, Jaipur, 17/09/16-21/09/16.
26. One week Academy Training Programme on Digital Hardware Design & FPGA, MNIT, Jaipur, 3/09/16-16/09/16.
27. One week Academy Training Programme on VLSI Digital Signal Processing Systems, MNIT, Jaipur, 23/01/16-27/01/16.
28. One week STTP on Advanced Digital Devices and Systems, MNIT, Jaipur, 28/03/15-01/04/15.
29. Online course on Signals and Systems organised by IIT Bombay. Durations two Weeks: 12/03/15-13/05/15.