Birla Institute of Technology, Mesra
   
Kalyan Koley
Assistant Professor, Electronics and Communication Engg
M.Tech. (National Institute of Technology, Silchar), PhD (Jadavpur University, Kolkata)
Contact Address
Permanent Address Hooghly, West Bengal
Local Address Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, Jharkhand 835215
Phone (Office) NA
Phone Residence NA
Email Id kalyan.koley@bitmesra.ac.in
Joined Institute on : 31-Aug-2021
  Work Experience
 
Teaching : 4.5 Years

Research : 1 Years

  Professional Background
  • Assistant Professor, Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, Jharkhand, India (August 2021 onward)
  • Assistant Professor (DST INSPIRE Faculty), Department of Electronics Engineering, Indian Institute of Technology (IIT), Dhanbad, Jharkhand, India (Feb 2017 – August 2021 )
  • Postdoctoral Researcher, University of California Berkeley - National Chaio Tung University (now National Yang Ming Chiao Tung University) joint research center I-RiCE Research Center, Hsinchu 300, Taiwan (Jun 2016 – Jan 2017 )
  • Postdoctoral Researcher, Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, India (Jan 2016 – May 2016 )
  • DST INSPIRE Fellow, Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, India (Dec 2011 – Dec 2015)
  • Guest Lecturer (SMDP-II Project), Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, India (Oct 2010 – Nov 2011)
  • Lecturer (SMDP II Project), Department of Electronics and Communication Engineering, National Institute of Technology, Silchar, India (Oct 2009 – Jul 2010)
  Research Areas
 
  • Modelling and simulations of MOSFET
  • CMOS circuit design for low power application
  • Analog VLSI circuit
  • Modelling and simulations of emerging MOSFET
  • Compact modeling of CMOS devices
     
  Award and Honours
 
  • DST INSPIRE Faculty Award, Department of Science and Technology, Government of India (July, 2016)
  • DST INSPIRE Fellowship, Department of Science and Technology, Government of India (2011-2015)
  • Ranked First, Master of Technology (Microelectronics and VLSI Design), National Institute of Technology, Silchar (2007-2009)
  • GATE Scholarship, Ministry of Human Resource Development, Government of India (2007-2009)
  • National Scholarship, Ministry of Human Resource Development, Government of India (2002-2006)

 IEEE Acknowledgement

  • Vice-Chairperson, IEEE Solid-State Circuits Society, Kolkata Section, India (2021-2023)
  • Treasurer, IEEE Solid-State Circuits Society, Kolkata Section, India (2019-2020)
  • Founding Secretary, IEEE Solid-State Circuits Society, Kolkata Section, India (2015-2016)
  • Treasurer, IEEE Electron Devices Society, Kolkata Section, India (2010-2012)
  • 2019 Technical Subcommittee Member, 2020 IEEE Electron Devices Technology and Manufacturing (EDTM 2020) Conference, Penang, Malaysia (one of the premier conference of IEEE Electron Devices Society)
   Publications
 

Journals Publications:

  1. Sayani Ghosh, Kalyan Koley, Samar K. Saha, and Chandan K. Sarkar, “Heterostructure Ge-Body pTFETs for Analog/RF Applications,” IEEE Journal of the Electron Devices Society, Volume 08, Pages1202 - 1209, September 2020.
  2. Bhubon C. Mech, Kalyan Koley, and Jitendra Kuumar, “Ge-GaAs-Ge Heterojunction MOSFETs for Mixed-Signal Applications,” IEEE Transactions on Electron Devices, Volume 67, Issue 9, Pages 3585 - 3591, September 2020.
  3. Sayani Ghosh, Kalyan Koley, and Chandan K. Sarkar, “Study of Circuit Performance and Non Quasi Static effect in Germanium Tunnel FET for different Temperatures,” Microelectronics Journal (Elsevier), Volume 90, Pages 204-210, August 2019.
  4. Bhubon C. Mech, Kalyan Koley, and Jitendra Kuumar, “The Understanding of SiNR and GNR TFETs for Analog and RF Application with Variation of Drain Doping Molar Fraction,” IEEE Transactions on Electron Devices, Volume 65, Issue 10, Pages 4694-4700, October 2018.
  5. Sayani Ghosh, Kalyan Koley, Chandan K. Sarkar, “A deep insight into Linearity and NQS parameters of Tunnel FET with emphasis on Lateral Straggle,” IET Micro & Nano Letters,  Volume 13, Issue 1, Pages 35-40, January 2018.
  6. Pradipta Dutta, Binit Syamal,  Kalyan Koley, N. Mohankumar, and Chandan K. Sarkar, “Short-channel drain current model for asymmetric heavily / lightly doped DG MOSFETs,”  Pramana  -  Journal of Physics (Springer), Volume 89, Issue 2, Pages 33(1-8), August 2017.
  7. Sayani Ghosh, Kalyan Koley, Samar K. Saha, and Chandan K. Sarkar, “High Performance Asymmetric Underlap Ge-pTFET with Pocket Implantation,”  IEEE Transactions on Electron Devices, Volume  63, Issue 10, Pages 3869-3875, October 2016.
  8. Sayani Ghosh, Kalyan Koley, and Chandan K. Sarkar, “Study of Process Induced Variability of Germanium-pTFET in Analog and RF Domain,” Microelectronics Reliability (Elsevier), Volume  65,  Pages  47-54,  October 2016.
  9. Arka Dutta, Kalyan Koley, Samar K. Saha and Chandan K. Sarkar, “Physical Insights of Electric Field Modulation in Dual–k Spacer Asymmetric Underlap FinFET,” IEEE Transactions on Electron Devices, Volume 63, Issue 8, Pages 3019-3027, August 2016.
  10. Pradipta Dutta, Kalyan Koley, Arka Dutta, and Chandan K. Sarkar, “An Analytical BTBT Current Model of Symmetric/Asymmetric 4T Tunnel Field Effect Transistors (DGTFET) with Ambipolar Characteristic,” IEEE Transactions on Electron Devices, Volume 63, Issue 7, Pages 2700-2707, July 2016. 
  11. Arka Dutta, Kalyan Koley, Samar K. Saha, Chandan K. Sarkar, “Impact of temperature on linearity and harmonic distortion characteristics of underlapped FinFET,” Microelectronics Reliability (Elsevier), Volume 61, Pages 99-105, June 2016. 
  12. Sagar Mukherjee, Kalyan Koley, Arka Dutta, and Chandan K. Sarkar, "Low-power amplitude modulator for wireless application using underlap double-gate metal–oxide–semiconductor field-effect transistor," IET Circuits, Devices & Systems, Volume 10, Issue 3, Pages 201-208, May 2016.
  13. Sagar Mukherjee, Swarnil Roy, Kalyan Koley, Arka Dutta, and Chandan K. Sarkar, “Design and Study of Programmable Ring Oscillator Using IDUDGMOSFET,” Solid-State Electronics (Elsevier), Volume 117, Pages 193–198, March 2016.
  14. Sagar Mukherjee, Swarnil Roy, Arka Dutta, Kalyan Koley, and Chandan K. Sarkar, “Impact of Lateral Straggle on Analog and Digital Circuit Performance using Independently Driven Underlap DG-MOSFET,” Microelectronics Journal (Elsevier), Volume 46, Issue 11, Pages 1082–1090, November 2015.
  15. Sayani Ghosh, Kalyan Koley, Samar K. Saha, and Chandan K. Sarkar, “Influence of the Gate Height Engineering on the Intrinsic Parameters of UDG-MOSFETs with Non Quasi Static Effect,” IEEE Journal of the Electron Devices Society, Volume 3, Issue 5, Pages 410-417, September 2015
  16. Pradipta Dutta, Binit Syamal, Kalyan Koley, N. Mohankumar, and Chandan K. Sarkar, “A New Threshold Voltage and Drain Current Model for Lightly/ Heavily Doped Surrounding Gate MOSFETs,” Journal of Computational and Theoretical Nanosciences (ASP), Volume 12, Issue 9, Pages 2515-2522, September 2015.
  17. Kalyan Koley, Arka Dutta, Samar K. Saha and Chandan K. Sarkar, “Analysis of High-κ Spacer Asymmetric Underlap DG-MOSFET for SOC Application,” IEEE Transactions on Electron Devices, Volume 62, Issue6, Pages 1733–1738, June 2015.
  18. Sayani Ghosh, Kalyan Koley, and Chandan K. Sarkar, “Impact of the Lateral Straggle on the Analog and RF Performance of TFET”, Microelectronics Reliability (Elsevier), Volume 55, Issue 2, Pages 326-331, February 2015. 
  19. Atanu Kundu, Kalyan Koley, Arka Dutta, and Chandan K. Sarkar, “Impact of Gate Metal Work-function Engineering for Enhancement of Subthreshold Analog/RF Performance of Underlap Dual Material Gate DG-FET,” Microelectronics Reliability (Elsevier), Volume 54, Issue 12, Pages 2717-2722, December 2014.
  20. Kalyan Koley, Arka Dutta, Samar K. Saha and Chandan K. Sarkar, “Effect of Source/Drain Lateral Straggle on Distortion and Intrinsic Performance of Asymmetric Underlap DG-MOSFETs,” IEEE Journal of the Electron Devices Society, Volume 2, Issue 6, Pages 135-144, November 2014. 
  21. Atanu Kundu, Arka Dutta, Kalyan Koley, Saptak Niyogy and Chandan K. Sarkar, “RF Parameter Extraction of UDG MOSFETs: A Look up Table Based Approach,” IET Circuits, Devices & Systems, Volume 8, Issue 6, Pages 554-560, November 2014. 
  22. Arka Dutta, Kalyan Koley, and Chandan K. Sarkar, “Impact of Underlap and Mole-Fraction on RF Performance of Strained-Si/Si1−xGex/Strained-Si DG MOSFETs,” Superlattices and Microstructures (Elsevier), Volume 75, Pages 634–646, November 2014. 
  23. Sudhansu Kumar Pati, Kalyan Koley, Arka Dutta, N. Mohankumar, Chandan K. Sarkar, “Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs,” Microelectronics Reliability (Elsevier), Volume 54, Issues 6–7, Pages 1137–1142, June–July 2014. 
  24. Arka Dutta, Kalyan Koley, and Chandan K. Sarkar, “Analysis of Harmonic Distortion in Asymmetric Underlap DG-MOSFET with High-k Spacer,” Microelectronics Reliability (Elsevier), Volume 54, Issues 6–7, Pages 1125-1132, June–July 2014. 
  25. Arka Dutta, Kalyan Koley, Samar K. Saha and Chandan K. Sarkar, “Analysis of Harmonic Distortion in UDG-MOSFETs,” IEEE Transactions on Electron Devices, Volume 61, Issue 4, Pages 998-1005, April 2014. 
  26. Sudhansu K. Pati, Kalyan Koley, Arka Dutta, N. Mohankumar and Chandan K. Sarkar “A new approach to extracting the RF parameters of asymmetric DG MOSFETs with the NQS effect,” Journal of Semiconductors (IOP), Volume 34, Issue 10, Pages 114002-5, 2013. 
  27. Kalyan Koley, Arka Dutta, Binit Saymal, Samar K. Saha and Chandan K. Sarkar, “Subthreshold Analog/RF Performance Enhancement of Underlap DG FETs with High-k Spacer for Low Power Applications”, IEEE Transactions on Electron Devices, Volume 60, Issue 1, Pages 63–69, January 2013. 
  28. Kalyan Koley, Binit Saymal, Atanu Kundu, N. Mohankumar and Chandan K. Sarkar, “Subthreshold Analog/RF Performance of Underlap DG FETs with Asymmetric Source/Drain Extensions,” Microelectronics Reliability (Elsevier), Volume 52, Issue 11, Pages 2572–2578, November 2012.

Conferences Publications :

  1. Ashish Maurya, Kalyan Koley, Jitendra Kumar, and Pankaj Kumar, " Calculation of OFF-Current of Tunnel FETs based on Subthreshold Swing: A New Approach," 2020 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), 2020,  Bangalore, India
  2. Sayani Ghosh, Kalyan Koley, Samar K. Saha, and Chandan K. Sarkar, "Non-Quasi-Static Effect on Ge-Body pTFET for Different Source Materials," 2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2020, Penang, Malaysia
  3. Kalyan Koley, Chandan K Sarkar, and Steve S. Chung, “Optimized Double-Gate MOSFET Structures for Analog and RF Performance Improvements,” The 2016 International Electron Devices and Materials Symposium (IEDMS 2016), November 24-25, 2016, Taipei, Taiwan.
  4. Sayani Ghosh, Kalyan Koley, and Chandan K. Sarkar, "Effect of temperature variability on RF performance of Germanium pTFET," 2016 3rd International Conference on Devices, Circuits and Systems (ICDCS), 3-5 March 2016, 2016, Coimbatore, India.
  5. Arka Dutta, Kalyan Koley, and Chandan K. Sarkar, “Impact of Temperature on Linearity and Harmonic Distortion Characteristics of Underlapped FinFET”, (Invited Talk), 8th International Conference on Materials for Advanced Technologies (ICMAT-2015), 28 June - 03 July, 2015, Suntec Singapore (Abstract Selection).
  6. Sayani Ghosh, Kalyan Koley, and Chandan K. Sarkar, “Study of Process Induced Variability of Germanium-p TFET in Analog and RF Domain”, 8th International Conference on Materials for Advanced Technologies (ICMAT-2015), 28 June - 03 July, 2015, Suntec Singapore (Abstract Selection)
  7. Arka Dutta, Kalyan Koley, and Chandan K. Sarkar, “Harmonic Distortion Analysis of Underlap Double Gate MOSFET with High-k Spacer for Improved Reliability of RF Performance”, (Invited Talk), 7th International Conference on Materials for Advanced Technologies (ICMAT-2013), 30 June - 05 July, 2013, Suntec Singapore (Abstract Selection).
  8. Sudhansu K. Pati, Kalyan Koley, Arka Dutta, N. Mohankumar and Chandan K. Sarkar, “Analysis of Deviations in RF Performance of Underlap Double Gate MOSFET Considering Variability in Body Thickness”, 7th International Conference on Materials for Advanced Technologies (ICMAT-2013), 30 June - 05 July, 2013, Suntec Singapore (Abstract Selection).
  9. Atanu Kundu, Binit Saymal, Kalyan Koley, N. Mohankumar and Chandan K. Sarkar, “RF Parameter Extraction of Bulk FinFETs: A Non Quasi Static Approach”, Proceeding 6th IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC 2010), December 15-17, 2010, Hong Kong.
  10. Saptak Niyogi, Kalyan Koley, Chandan K. Sarkar and Saumuya Pandit, “Small Signal Modelling and Parameter Extraction Technique for Overlap and Underlap Double Gate MOSFET for RF Circuit Design”, Proceeding MOS-AK/GSA Workshop, 16-17 March, 2012, New Delhi, India.
  11. Amretashis Sengupta, Kalyan Koley and Chandan K. Sarkar, “Subthreshold charge leakage in nanoparticle embedded DGMOSFET memory devices an analytical study”, 2012 International Conference on Devices, Circuits and Systems (ICDCS), 15-16 March 2012, Coimbatore, India.
  12. Satyananda Namana, Srimanta Baishya, and Kalyan Koley, “A Subthreshold Surface Potential Modeling of Drain/Source Edge Effect on Double Gate MOS Transistor”, Proceeding IEEE International Conference on Electronics and Information Engineering (IEEE ICEIE 2010), August 1-3, 2010, Kyoto, Japan.
  13. Kalyan Koley and Srimanta Baishya, “A Subthreshold Surface Potential Modeling of Drain/Source Edge Effect on MOS Transistor”, Proceeding 3rd IEEE International Conference on Computer Science and Information Technology (IEEE ICCSIT 2010), July 9-11, 2010, Chengdu, China.  
  Member of Professional Bodies
 
  • Senior Member, IEEE
  Current Sponsored Projects
 
  • Name of the Project: RF, Noise, and Harmonic Distortion Analysis of Structurally Modified Germanium on Insulator MOSFETS
    Funding Agency: Department of Science and Technology, Government of India
    Project Cost: Rs. 35,00,000/- (Thirty Five Lakhs)
    Duration: 5 years (February 2017 – January 2022)
  Member, Editorial Board
 
  • Associate Editor, IEEE Access (2017 – till date)
  • Moderator, IEEE TechRxiv (2020 – till date)