Birla Institute of Technology, Mesra
   
Deepti Gola
Assistant Professor, Electronics and Communication Engg
B.Tech. (U. P. Technical University), M.Tech. (Banasthali University Rajasthan), Ph.D (I.I.T. Patna)
Contact Address
Permanent Address 208-A Balajipuram, Shahganj, Agra, UP - 282010
Local Address House No. TA-8, Birla Institute of Technology Mesra, Ranchi, Jharkhand - 835215
Phone (Office) 9411926012
Phone Residence 9955532517
Email Id deeptigola@bitmesra.ac.in
Joined Institute on : 6-Sep-2021
  Research Areas
 

Microelectronics, Advanced Semiconductor Device Modeling, Nanoscale Devices and Circuits

  Award and Honours
 

Reviewer of IEEE Transactions on Semiconductor Manufacturing, IEEE Transactions on Electron Devices, Semiconductor Science and Technology, Sensors and Actuators: A Physical, International Journal of Electronics and Device Physics, Journal of Nanoelectronics and Optoelectronics, International Journal of Electronics and Communication, Silicon Journal, IETE Technical Review.

   Publications
 

International Journal Papers

  1. Deepti Gola, B. Singh, P.S.T.N. Srinivas and P. K. Tiwari, “Thermal Noise Models for Tri-gate Junctionless Transistors Including Substrate Bias Effects”, IEEE Transactions on Electron Devices, vol. 67, no. 1, pp. 263-269, Jan. 2020, DOI: 10.1109/TED.2019.2953084.  (Impact Factor: 2.913).
  2. Deepti Gola, B. Singh, J. Singh, S. Jit and P. K. Tiwari, “Static and Quasi-Static Drain Current Modeling of Tri-Gate Junctionless Transistor with Substrate Bias Induced Effects”, IEEE Transactions on Electron Devices, vol.66, no.7,pp.2876-2883,  July 2019, DOI: 10.1109/TED.2019.2915294.   (Impact Factor: 2.913).
  3. Deepti Gola, B. Singh and P. K. Tiwari, “Subthreshold Characteristic Analysis and Models for Tri-Gate SOI MOSFETs Using Substrate Bias Induced Effects,” IEEE Transactions on Nanotechnology, vol. 18, pp. 329-335, 2019, DOI: 10.1109/TNANO.2019.2906567. (Impact Factor: 2.57)
  4. Deepti Gola, B. Singh and P. K. Tiwari, “Subthreshold Modeling of Tri-Gate Junctionless Transistors with Variable Channel Edges and Substrate Bias Effects”, IEEE Transactions on Electron Devices, vol. 65, no. 5, pp. 1663–1671, May 2018, DOI: 10.1109/TED.2018.2809865 (Impact Factor: 2.913).
  5. Deepti Gola, B. Singh and P. K. Tiwari, “A Threshold Voltage Model Of Tri-gate Junctionless Field-effect Transistors Including Substrate Bias Effects”, IEEE Transactions on Electron Devices, vol. 64, no. 9, pp. 3534–3540, Sep. 2017, DOI: 10.1109/TED.2017.2722044  (Impact Factor: 2.913).
  6. Deepti Gola, B. Singh and P. K. Tiwari “Self-heating and Negative Differential Conductance Improvement by Substrate Bias Voltage in Tri-gate Junctionless Transistor”, Silicon, 2021 (Impact Factor: 2.67).
  7. B. Singh, Deepti Gola , K. Singh, E. Goel, S. Kumar and S. Jit “2-D Analytical Threshold Voltage Model for Dielectric Pocket Double-Gate Junctionless FETs by Considering Source/Drain Depletion Effects ,” IEEE Transactions on Electron Devices, vol. 64, no. 3, pp. 901–908, 2017, DOI: 10.1109/TED.2016.2646460 (Impact Factor: 2.913).
  8. B. Singh, Deepti Gola, K. Singh, E. Goel, S. Kumar, and S. Jit “Analytical modeling of subthreshold characteristics of ion-implanted symmetric double gate junctionless field effect transistors,” Materials Science in Semiconductor Processing, vol. 58, pp. 82–88, 2017. doi.org/10.1016/j.mssp.2016.10.051 (Impact Factor: 3.927).
  9. B. Singh, Deepti Gola, K. Singh, E. Goel, S. Kumar, and S. Jit, “Analytical Modeling of Channel Potential and Threshold Voltage of Double-Gate Junctionless FETs With a Vertical Gaussian-Like Doping Profile,” IEEE Trans. Electron Devices, vol. 63, no. 6, pp. 2299–2305, 2016, DOI: 10.1109/TED.2016.2556227 (Impact Factor: 2.913).
  10. B. Singh, Deepti Gola, E. Goel, S. Kumar, K. Singh, and S. Jit, “Dielectric pocket double gate junctionless FET: a new MOS structure with improved subthreshold characteristics for low power VLSI applications,” J. Comput. Electron., vol. 15, no. 2, pp. 502–507, 2016, DOI: 10.1007/s10825-016-0808-3 (Impact Factor: 1.807).
  11. Y. S. Duksh, B. Singh, Deepti Gola, P. K. Tiwari, S. Jit, “Subthreshold Modeling of Graded Channel Double Gate Junctionless FETs”, Silicon, 2020. https://doi.org/10.1007/s12633-020-00514-1 (Impact Factor: 2.67).
  12. B. Singh, T. N. Rai, Deepti Gola, K. Singh, E. Goel, S. Kumar, P. K. Tiwari, S. Jit, “Ferro-electric stacked gate oxide heterojunction electro-statically doped source/drain double-gate tunnel field effect transistors: A superior structure”, Materials Science in Semiconductor Processing, vol. 71, pp. 161-165, 2017, doi.org/10.1016/j.mssp.2017.07.014 (Impact Factor: 3.927).

 

Conference Papers

  1.  Deepti Gola, B. Singh and P. K. Tiwari, “Analytical Modeling of  Analog/RF Parameters for Tri-gate Junctionless Field Effect Transistor Incorporating Substrate Biasing Effects”, Proceedings IEEE TENCON 2019, Kochi, India, pp.1838 - 1841, 17-20th Oct. 2019.
  2. Deepti Gola, B. Singh and P. K. Tiwari, Investigation of Thermal Noise in Tri-gate Junctionless Transistor, Proceedings IEEE International Conference on Electrical, Electronics and Computer Engineering (UPCON-2019), Aligarh, India, pp. 1-5, 8-10th Nov. 2019.
  3. B. Singh, Deepti Gola, and S. Jit, Subthreshold Performance Analysis of Double-Fin Multi-channel Junctionless Transistor with Substrate Bias Effects”, Proceedings IEEE TENCON 2019, Kochi, India, pp.1834 - 1837, 17-20th Oct. 2019.
  4. B. Singh, Deepti Gola, Kunal Singh, Ekta Goel, Sanjay Kumar, and Satyabrata Jit, “Temperature Sensitivity Analysis of Double Gate Junctionless Field Effect Transistor with Vertical Gaussian Doping Profile,” Proceedings IEEE International Conference on Micro-Electronics and Telecommunication Engineering (ICMETE), 2016, pp. 675–679. DOI: 10.1109/ICMETE.2016.127
  5. B. Singh, Deepti Gola, Kunal Singh, Ekta Goel, Sanjay Kumar, and Satyabrata Jit, “Performance Evaluation of Double Gate Junctionless Field Effect Transistor with Vertical Gaussian Doping Profile,” Proceedings IEEE International Conference On Recent Trends In Electronics Information Communication Technology (RTEICT), 2016, pp. 769–772. DOI: 10.1109/RTEICT.2016.7807930
  6. S. Bhushan, A. Kumar, Deepti Gola and P. K. Tiwari, "An analytical subthreshold current model of short-channel symmetrical double gate-all-around (DGAA) field-effect-transistors," 2017 Devices for Integrated Circuit (DevIC), Kalyani, 2017, pp. 211-215, DOI: 10.1109/DEVIC.2017.8073938.